This invention relates to integrated circuits, particularly to static random access memory (SRAM) devices, in either embedded form or stand alone (i.e. discrete) form.
As integrated circuits (ICs) become physically larger and more complex, the amount of power used by an IC increases. Power consumption in an IC may increase for several reasons. For example, the frequency at which an IC switches consumes power by charging and discharging capacitance on the IC. Increasing the switching frequency increases the power consumed on an IC. Power may also be consumed due to DC (direct current) conditions such as leakage in transistors and voltage dropped across resistors.
Power reduction may be achieved by reducing power supply voltages provided to the IC. For example, the voltage applied to an SRAM (Static Random Access Memory) may be reduced when the SRAM is not being accessed. Power reduction is particularly important in the design of DSP (Digital Signal Processor) ICs with large memory arrays. The power used by large memory arrays may be reduced by putting them into a “sleep” mode or a “retain” mode where the voltage applied to the array is reduced. However, some of the data in some ICs may be lost during retention due to process non-idealities such as defects and parametric variations.
To prevent data for an end user from being lost while in the retain mode, it is important to be able to test SRAM arrays, while in the retain mode, before being deployed to the end user. It is also important that the time taken to test SRAM arrays while in the retain mode be relatively short.